n2812nk 20121115-s00004 /53012 sy 20120522-s00007 no.a2065-1/7 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 LV8163QA overview the LV8163QA is a driver ic for single phase fan motor which operates noiselessly by btl linear output method. the LV8163QA has variable speed function that corresponds to external pwm single input. therefore, this ic is suitable for cpu cooler for note pc and the like which requires low power consumption, noiseless operation and variable speed functions. functions ? single phase full wave drive by btl output method. ? hall bias output pin. ? speed control function by pwm input. ? startup support function (100% dutystart) ? integrated lock protector and auto recovery circuit. ? fg signal pin, rd signal pin ? standby mode and quick start function. ? integrated tsd (thermal shutdown) circuit specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit power supply voltage v cc max 7 v output pin current i out max 0.7 a output pin withstand voltage v out max 7 v hb output current i hb max 10 ma pwm pin voltage v pwm max 7 v fg/rd pin sink current i fg /i rd max 5 ma fg/rd output pin voltage v fg /v rd max 7 v allowable power dissipation pd max mounted on specified board *1 1050 mw operating temperature topr -30 to +95 c storage temperature tstg -55 to +150 c *1 specified substrate : 105mm 120mm 1.6mm, two-sided glass epoxy board *2 do not exceed tjmax = 150 c caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of th e ic may be degraded. please contact us for the further detai ls. bi-cmos ic fan motor driver single-phase full-wave driver orderin g numbe r : ena2065a stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV8163QA no.a2065-2/7 operating conditions at ta = 25 c parameter symbol conditions ratings unit power supply voltage vcc 5.0 v operating power supply voltage vccop 2.0 to 6.0 v hall input common-mode input voltage range vicm 0.2 to v cc -1.2 v pwm pin input frequency fpwmin 20 to 60 khz electrical characteristics at ta = 25c, v cc = 5v ratings parameter symbol conditions min typ max unit i cc during operation 0.95 1.3 1.6 ma circuit current i cc st during standby mode 10 30 a hb pin voltage v hb i hb = 5ma 0.9 1.03 1.2 v output pin high-level voltage v o h i out = 200ma (v cc ? v out ) 0.16 0.23 v output pin low-level voltage v o l i out = 200ma 0.10 0.15 v hall amplifier input offset voltage v in ofs -6 6 mv hall amplifier voltage gain gh 44 45.5 47 db pwm pin input low level voltage vpwml 0 v cc 0.2 v vcc < 4v 1.8 6.0 v pwm pin input high level voltage vpwmh 4v vcc v cc 0.45 6.0 v fg/rd pin low-level voltage v fg l/v rd l i fg /i rd = 3ma 0.3 v fg/rd pin leak current i fg l/i rd l v fg /v rd = 7v 10 a fg comparator hysteresis width fghys 8 16 mv lock-detection output on ti me lt1 0.4 0.6 0.8 sec lock-detection output off time lt2 4 6 8 sec lock-detection output on/off ratio lrto lrto=lt2/lt1 8 10 12 thermal shutdown operating temperature tsd design guarantee * 180 c thermal shutdown hysteresis width tsd design guarantee * 30 c * design target: these values are the target value in designs. the parameters are not measured independently. pin assignment truth value table in1 in2 pwm out1 out2 fg rd mode high high low operation (out2 out1) low low low recirculation high low * low off off off lock protector (see *1) high high low operation (out1 out2) low low low recirculation low high * off low low off lock protector (see *1) * low low low off low standby (see *2) *1 if fg pulse is not switched when lock detect ion output is on, lock protecdtor mode is set. *2 standby mode is set when time of lock protecdtor + pwm input low level voltage is greator than 750 s. standby mode is set when time of low level voltage is 750 s and voltage is supplied and pwm input is at low level voltage. 1 in1 2 3 4 5 10 rd 9 hb fg 8 v cc 7 gnd 6 out1 top view in2 pwm out2
LV8163QA no.a2065-3/7 package dimensions unit : mm (typ) 3432 block diagram sanyo : udfn10(2.6x2.6) 2.6 2.125 2.6 1.235 0.2 min 0.35 15 10 12 6 0.55 max 0 to 0.05 0.127 0.25 0.5 top view side view bottom view pd max -- ta 0 1.0 0.5 1.5 --30 0 90 60 30 120 0.46 1.05 ambient temperature, ta -- c ambient temperature, pd max -- w specified board (105 120 1.6mm 3 , paper phenol) 1 in1 2 hb 3 in2 4 out1 5 out2 10 9 8 7 6 gnd rd fg v cc pwm tsd control osc + - + - + - + - hb 500k 10k v cc lock detection
LV8163QA no.a2065-4/7 example of circuit application *1 < capacitor for power stabilization > the capacitor fo r power stabilization must be 1 f or greater. the capacitor is not removable. make sure to connect the capacitor with the think and shortest possible pattern between v cc and gnd. when a protection diode against reverse connection is used. if supply voltage increases due to coil kickback, connect zener diode between power supply and gnd. this ic performs synchronous rectification to reduce hest generation and to enhance efficiency. depends on usage conditions, coil current may flow back to power supply by synchronous rectification. *when output duty is reduced rapidly. *when pwm input frequency is low. the increase of supply voltage varies depends on the presence of diode (to prevent ic descruction from reverse connection), the size of power capacitor, and usage fan. if the increase of supp ly voltage is excessive, use capacitor with enough capacitance or connect zene r between power supply and gnd so that the voltage is within the absolute maximum ratings. *2 < hb pin > constant voltage output pin, which is used as bias for hall element. when hall element is biased from vcc line and hb pin is unused, hb pin should be pulled down to gnd with resistor of 1k ? . bias for power supply and bias for hb pin cannot be used together. connect a resistor between hall element and gnd to adjust amplitude of hall element. *3 < in1,in2 pin > hall element signal input pin. make sure to keep the wiring short to prevent noise. if noise is generated, use capacitor between in1 and in2. as for hall input level, the following conditions must be met: difference of voltage between in1 and in2 > usage voltage / hall amplifier gain + hall amplifier input offset 1 2 3 4 5 10 pwm 9 8 v cc 7 6 in1 h *3 *2 *1 hb in2 out1 gnd out2 fg rd *6 *5 *4 rdout fgout *7 pwmin
LV8163QA no.a2065-5/7 *4 < pwm pin > motor speed control sifnal input pin. pwm pin is pulled up at 500k ? in lv8136qa. resistance of 500k ? is used for full-speed setting when pwm pin is open. in order to control motor speed using open collector input method (open drain), pull-up is required using suitable resistance. pull-up resistance is not required when motor speed is controlled by push-pull input method. the order of power supply is optinal; either to power su pply voltage or pwm input, under one of the following conditions. 1) when open collector input method is used. 2) pull-up resistance is not implemented and push-pull input method is used. it is recommended to connect a resistance greator than 1k ? in series to protect pwm pin against open gnd and misconnection. *5 < fg pin > used as rotation counter. this pin is open drain output. you can count rotations according to phase change. this pin is set to off during standby mode. make sure to set this pin open when unused. it is recommended to connect a resistance greater than 1k ? in series to protect pwm pin against open gnd and misconnection. *6 < rd pin > used as lock detector. this pin is open drain output. during rotation, rd pin is set to low-level voltage. during lock detection, it is set to off. during standby, it is set to low-level voltage. make sure to set this pin open when unused. it is recommended to connect a resistance greator than 1k ? in series to protect pwm pin against open gnd and misconnection. *7 < low power dissipation during standby > during standby, the fan motor used in lv8136qa can reduce power dissipation into 10a (under room temperature, typ). however, power dissipation cannot be reduced into 10a under the following conditions. ? when bias of hall element is supplied from power supply: current flowing into hall element increases. ? when pull-up resistor is used to pwm pin during standby, the current flowing in to pull-up resistor increases because pwm pin must be set to low-level voltage. ? when using rd pin during standby, the current flowing into pull-up resistor increases because rd pin turns low-level voltage.
LV8163QA no.a2065-6/7 timing chart switch: stand-by/operation *1 t slp =750 s(typ) *2 if pwm signal is low-level voltage for the period of t slp and fg signal is not switched for the period of lt1, the mode is set to standby. when turning on power, if pwm signal is low-level voltage for the period of t slp , the mode is set to standby. *3 during standby mode, fg pin is set to off and rd pin is set to low^level voltage. lock protector *1 when lock protector is in operation, out1 and out2 are both set to low-level voltage. *2 rd is set to off during the period of lock protection. after lock protector is cance lled, rd is set to low-level voltage when fg switches from off to l or l off. *3 if pwm = low-level voltage is inputted for the period of t slp during lock protection, the mode is set to standby. *4 the operations start at 100% du ty when turning on the power, cancelling lock protection, or recovering from standby mode. ( switch of fg between off l and l off takes place for 5 or 6 times) v cc pwm hb t slp t slp fg in2 in1 active stand-by active stand-by active waiting for fg pulse lt1 out1 in1 out2 fg in2 rd constraint by fan cancellation of fan constraint power on power off power on waiting for fg pulse lt1 lock protection lt2 restart fg detection
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